When a digital to analog converter (DAC) converts the input digital bits into an analog output, each bit is assigned a weight. The sum of all weighted bits is then the analog output. However, the weights typically are not exactly the desired values. For example, although weights of 4, 2 and 1 are desired, they may actually be 3.4, 2.25 and 1.25. The result is that the analog output may not always increase as the digital input increases.
The problem is most pronounced at “major carry” transitions in the input code, as exemplified by the midscale transition between input code [0,1,1, . . . , 1,1] and [1,0,0, . . . , 0,0]. As the number of bits increase, the tolerances on individual bit weights decreases. More stringent tolerances on bit weights increase the cost of DACs and can limit the number of bits a DAC can accept. A corollary consequence is precision control based on non-monotonic DACs is difficult to ensure.
Previously known approaches to building precision DACs with more than 12 bits required very precise component matching and/or calibration to maintain monotonicity. More than 12 bits would require expensive or even unrealistic component tolerances. An alternative solution offering a guaranteed monotonic DAC used a thermometer code for the most significant bits and dithered the least significant bits. While this design may guarantee monotonicity, it may not allow the precise analog control desired in some applications.
A DAC is needed with a monotonic output at all transitions. Such a DAC should be extendable to a large number of bits without requiring components with unusually stringent tolerances.